Back to results
US 2026/0314504 A1Published application
Semiconductor package including power supply capacitor
AssigneeSamsung Electronics Co., Ltd.
InventorKilsoo KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip, an upper semiconductor chip stacked on the uppermost second semiconductor chip among the plurality of second semiconductor chips, and a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor. The upper semiconductor chip includes an upper through via that passes through at least a portion of the upper semiconductor chip and is electrically connected to the capacitor.
Claims20
A semiconductor package comprising:
- a first semiconductor chip;
- a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip;
- an upper semiconductor chip stacked on an uppermost second semiconductor chip among the plurality of second semiconductor chips;
- and
- a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor,
- wherein the upper semiconductor chip comprises an upper through via electrically connected to the capacitor.
3 more elements
A semiconductor package comprising:
- a first semiconductor chip;
- a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip;
- a connection terminal disposed on a lower surface of the first semiconductor chip;
- an upper semiconductor chip stacked on an uppermost second semiconductor chip among the plurality of second semiconductor chips;
- a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor;
- and
- a molding layer surrounding the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip,
- wherein each of the plurality of second semiconductor chips comprises a plurality of second through vias including a power/ground through via, and
- wherein the upper semiconductor chip comprises an upper semiconductor substrate and an upper through via disposed in the upper semiconductor substrate.
6 more elements
A semiconductor package comprising:
- a first semiconductor chip;
- a connection terminal disposed on a lower surface of the first semiconductor chip;
- a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip;
- an upper semiconductor chip stacked on an uppermost second semiconductor chip among the plurality of second semiconductor chips;
- a dummy semiconductor chip comprising a dummy semiconductor substrate stacked on the upper semiconductor chip, a dummy bonding layer, and a capacitor disposed between the dummy semiconductor substrate and the dummy bonding layer;
- and
- a molding layer surrounding the plurality of second semiconductor chips, the upper semiconductor chip, and the dummy semiconductor chip,
- wherein the first semiconductor chip comprises:
- a first semiconductor substrate;
- a first bonding layer on a lower surface of the first semiconductor substrate;
- a second bonding layer on an upper surface of the first semiconductor substrate;
- and
- a plurality of first through vias disposed in the first semiconductor substrate,
- wherein each of the plurality of second semiconductor chips comprises:
- a second semiconductor substrate;
- a second chip wiring layer;
- a plurality of second through vias disposed in the second semiconductor substrate;
- a third bonding layer on a lower surface of the second semiconductor substrate;
- and
- a fourth bonding layer on an upper surface of the second semiconductor substrate,
- wherein the plurality of second through vias comprise:
- a power/ground through via;
- and
- a signal through via, and
- wherein the upper semiconductor chip comprises:
- an upper semiconductor substrate;
- a first upper bonding layer in contact with the uppermost second semiconductor chip;
- a second upper bonding layer in contact with the dummy semiconductor chip;
- and
- an upper through via disposed in the upper semiconductor substrate.
27 more elements
Dependencies are inferred from the claim text.