Back to results
US 2026/0314496 A1Published application
Microelectronic assemblies
AssigneeIntel Corporation
InventorsShawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
Life of this patent
Estimating the term…
Abstract
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
Claims20
A microelectronic assembly, comprising:
- a package substrate;
- a first die having a top side above a bottom side, the bottom side of the first die coupled to the package substrate by first interconnects, the first die having a through substrate via (TSV) therein;
- a second die having a top side above a bottom side, the bottom side of the second die coupled to the top side of the first die by second interconnects, and the bottom side of the second die coupled to the package substrate by third interconnects, the third interconnects laterally spaced apart from the first die;
- a third die having a top side above a bottom side, the third die laterally spaced apart from the second die, the bottom side of the third die coupled to the top side of the first die by fourth interconnects, the bottom side of the third die at a same level as the bottom side of the second die, and the top side of the third die below the top side of the second die;
- and
- a fourth die having a top side above a bottom side, the fourth die laterally spaced apart from the third die, the bottom side of the fourth die coupled to fifth interconnects, the bottom side of the fourth die higher above the package substrate than the bottom side of the first die, and the top side of the fourth die higher above the package substrate than the top side of the first die, wherein there is no additional die vertically intervening between the fourth die and the package substrate, and wherein a horizontal plane intersects the second die, the third die and the fourth die.
3 more elements
A microelectronic assembly, comprising:
- a package substrate;
- a first die having a top side above a bottom side, the bottom side of the first die coupled to the package substrate by first solder structures, the first die having a through substrate via (TSV) therein;
- a second die having a top side above a bottom side, the bottom side of the second die coupled to the top side of the first die by second solder structures, and the bottom side of the second die coupled to the package substrate by interconnects, the interconnects laterally spaced apart from the first die;
- a third die having a top side above a bottom side, the third die laterally spaced apart from the second die, the bottom side of the third die coupled to the top side of the first die by third solder structures, the bottom side of the third die at a same level as the bottom side of the second die, and the top side of the third die below the top side of the second die;
- and
- a fourth die having a top side above a bottom side, the fourth die laterally spaced apart from the third die, the bottom side of the fourth die coupled to fourth solder structures, the bottom side of the fourth die higher above the package substrate than the bottom side of the first die, and the top side of the fourth die higher above the package substrate than the top side of the first die, wherein there is no additional die vertically intervening between the fourth die and the package substrate, and wherein a horizontal plane intersects the second die, the third die and the fourth die.
3 more elements
A method of fabricating a microelectronic assembly, the method comprising:
- providing a package substrate;
- providing a first die having a top side above a bottom side, the bottom side of the first die coupled to the package substrate by first interconnects, the first die having a through substrate via (TSV) therein;
- providing a second die having a top side above a bottom side, the bottom side of the second die coupled to the top side of the first die by second interconnects, and the bottom side of the second die coupled to the package substrate by third interconnects, the third interconnects laterally spaced apart from the first die;
- providing a third die having a top side above a bottom side, the third die laterally spaced apart from the second die, the bottom side of the third die coupled to the top side of the first die by fourth interconnects, the bottom side of the third die at a same level as the bottom side of the second die, and the top side of the third die below the top side of the second die;
- and
- providing a fourth die having a top side above a bottom side, the fourth die laterally spaced apart from the third die, the bottom side of the fourth die coupled to fifth interconnects, the bottom side of the fourth die higher above the package substrate than the bottom side of the first die, and the top side of the fourth die higher above the package substrate than the top side of the first die, wherein there is no additional die vertically intervening between the fourth die and the package substrate, and wherein a horizontal plane intersects the second die, the third die and the fourth die.
3 more elements
Dependencies are inferred from the claim text.