US 2026/0314489 A1 · INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.

Claims20

Dependent claims

A package comprising:

a first die over and bonded to a wafer, wherein a first dielectric layer of the first die is directly bonded to a second dielectric layer of the wafer, wherein the first die comprises:
a bottom portion of the first die;
and
a top portion of the first die, wherein the top portion extends laterally beyond sidewalls of the bottom portion of the first die by a width that is up to 5 µm, wherein a corner region of the bottom portion of the first die comprises:
a first sidewall;
a second sidewall connected to the first sidewall;
and
a third sidewall connected to the first sidewall, wherein a first angle between the first sidewall and the second sidewall is greater than 90°;
through substrate vias (TSVs) extending through a portion of the wafer;
and
a redistribution structure on a backside of the wafer, wherein the redistribution structure is electrically connected to the first die through the TSVs.

8 more elements

Dependencies are inferred from the claim text.

Integrated circuit package and method

Life of this patent

Integrated circuit package and method

Life of this patent

Abstract

Claims20