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US 2026/0314486 A1Published application
Three-dimensional chip stack with backside power distribution network
AssigneeInternational Business Machines Corporation
InventorsXiaoli He, Joshua Mark Rubin, Tao Li, Ruilong Xie, Qianwen Chen
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Abstract
A semiconductor structure is provided which includes a 3D chip stack including a bottom chip and a top chip having a backside power distribution network (BSPDN) in which the top chip is hybrid bonded to the bottom chip and where the top chip and bottom chip are electrically connected to a packaging substrate. The electrical connection can be through a metal wire, a metal clip or any combination thereof.
Claims18
A semiconductor structure comprising:
- a bottom chip comprising a semiconductor substrate, a first front-end-of-line (FEOL) level and a first back-end-of-line (BEOL) structure;
- a top chip comprising a second FEOL level located between a second BEOL structure and a backside power distribution network (BSPDN) structure, wherein a hybrid bonding interface is present between the first BEOL structure of the bottom chip and the second BEOL structure of the top chip;
- and
- a packaging substrate attached to the semiconductor substrate of the bottom chip, wherein the top chip and the bottom chip are independently electrically connected to the package substrate.
1 more element
Dependencies are inferred from the claim text.