Low resistance structures in systems
AssigneeMicron Technology, Inc.
InventorsBharat Bhushan, Fuad Badrieh, Mark Zaleski, Kunal R. Parekh, Keizo Kawakita, Akshay N. Singh
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AssigneeMicron Technology, Inc.
InventorsBharat Bhushan, Fuad Badrieh, Mark Zaleski, Kunal R. Parekh, Keizo Kawakita, Akshay N. Singh
Estimating the term…
Methods, systems, and devices for low resistance structures in systems are described. The described techniques provide for various structures of a power delivery network (PDN), each associated with a reduced resistance relative to other PDN structures. The PDN may include multiple through silicon vias (TSVs) having a relatively small footprint coupled with a metallic pad, where the TSVs may have a relatively small pitch between adjacent ones of the TSVs. In some examples, the PDN structure may include layers between the multiple TSVs and the metallic pad, where each metal layer may be separated by a respective set of vias including various conductive materials. In some other examples, the PDN structure may include a through dielectric via (TDV) between the TSVs and the metallic pad or may include respective sets of metal bars between metallic pads coupled with the TSVs.
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Dependencies are inferred from the claim text.