Semiconductor package including connecting pads

A method of manufacturing a semiconductor package, the method comprising:

• providing a carrier substrate;
• forming a passivation film on the carrier substrate, the passivation film including an opening;
• forming a connecting pad including a first portion and a second portion on the first portion, the first portion disposed inside the opening of the passivation film, the second portion disposed on the first portion;
• forming a post on the second portion of the connecting pad;
• mounting an element on the second portion of the connecting pad, the element including an element pad on an upper surface thereof;
• forming a mold layer on the passivation film, the mold layer wrapping the second portion of the connecting pad, the post, and the element;
• forming a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern electrically connected to the post and the element pad;
• mounting a semiconductor chip on the wiring structure;
• removing the carrier substrate to expose a lower surface of the first portion of the connecting pad;
• and
• forming a solder ball on the lower surface of the first portion of the connecting pad that has been exposed in the removing,
• wherein the second portion of the connecting pad is in contact with the element, and
• wherein a width of the second portion of the connecting pad in a first direction parallel to an upper surface of the passivation film is greater than a width of the first portion of the connecting pad in the first direction.

A method of manufacturing a semiconductor package, the method comprising:

• forming a passivation film on a first carrier substrate;
• forming a connecting pad having a T shape, the T shape including a first portion penetrating the passivation film and a second portion on the first portion, the second portion having a width in a first direction parallel to an upper surface of the passivation film greater than a width of the first portion in the first direction, the connecting pad including a barrier film and a filling film on the barrier film;
• forming a post on the second portion of the connecting pad;
• mounting an element on the second portion of the connecting pad, an adhesive layer being disposed between the passivation film and the element, the element including an element pad on an upper surface thereof;
• forming a first mold layer on the passivation film to wrap the second portion of the connecting pad, the post, the element, and the element pad;
• performing a planarization process on the first mold layer such that an upper surface of the first mold layer, an upper surface of the post, and an upper surface of the element pad are on a same plane;
• forming a first wiring structure on the first mold layer, the first wiring structure including a first insulating layer and a first wiring pattern electrically connected to the post and the element pad;
• mounting a first semiconductor chip on the first wiring structure through a first solder ball, the first semiconductor chip overlapping at least a part of the element in a second direction perpendicular to the upper surface of the passivation film;
• forming a second mold layer on the first wiring structure covering the first semiconductor chip;
• attaching a second carrier substrate on the second mold layer;
• removing the first carrier substrate to expose a lower surface of the first portion of the connecting pad;
• and
• forming a second solder ball on the lower surface of the first portion of the connecting pad that has been exposed in the removing.