Integrated circuit packages and methods of forming the same

A device comprising:

• an interposer comprising through-substrate vias;
• a redistribution structure comprising:
• a first dielectric layer over the interposer, the first dielectric layer having a first width between first sidewalls of the first dielectric layer in a cross-sectional view;
• a first metallization pattern extending along and through the first dielectric layer, the first metallization pattern comprising redistribution lines, the redistribution lines contacting the through-substrate vias;
• and
• a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer having a second width between second sidewalls of the second dielectric layer in the cross-sectional view, the second width being less than the first width, portions of a top surface of the first dielectric layer being exposed by the second dielectric layer, the portions of the top surface extending between the first sidewalls of the first dielectric layer and the second sidewalls of the second dielectric layer.

A device comprising:

• a package substrate;
• a package component attached to the package substrate, the package component comprising:
• a semiconductor substrate;
• through-substrate vias in the semiconductor substrate;
• a lower dielectric layer on the semiconductor substrate;
• a metallization pattern on the lower dielectric layer, the metallization pattern comprising redistribution lines connected to the through-substrate vias and a seal ring surrounding the redistribution lines in a top-down view, the seal ring being electrically isolated from the redistribution lines;
• and
• an upper dielectric layer on the metallization pattern and the lower dielectric layer, the upper dielectric layer covering a top surface of the seal ring, sidewalls of the lower dielectric layer extending laterally beyond sidewalls of the upper dielectric layer;
• and
• an integrated circuit device attached to the package component, the through-substrate vias electrically connecting the integrated circuit device to the metallization pattern.