Semiconductor chip, chip stacked structure and semiconductor package including the same

A chip stacked structure, comprising:

• a first semiconductor chip comprising a first substrate, a first device layer on the first substrate, and a first front side wiring structure on a front surface of the first device layer;
• a second semiconductor chip comprising a second substrate, a second device layer on the second substrate, and a second front side wiring structure on a front surface of the second device layer, the second semiconductor chip being stacked on the first semiconductor chip;
• a through electrode penetrating at least a portion of the first semiconductor chip;
• and
• a through heat-dissipation film surrounding at least a portion of the through electrode,
• wherein the first front side wiring structure comprises:
• a first front side via layer comprising a first front side via, the first front side via layer being disposed on the first device layer,
• a first front side metal layer comprising a first front side wiring, the first front side metal layer being disposed on the first front side via layer, and
• a first front side heat-dissipation structure comprising a first portion surrounding a bottom surface and a side surface of the first front side via, and
• wherein the second front side wiring structure comprises:
• a second front side via layer comprising a second front side via, the second front side via layer being disposed on the second device layer,
• a second front side metal layer comprising a second front side wiring, the second front side metal layer being disposed on the second front side via layer, and
• a second front side heat-dissipation structure comprising a first portion surrounding a bottom surface and a side surface of the second front side via.

A semiconductor package, comprising:

• a package substrate;
• and
• a chip stacked structure disposed on the package substrate,
• wherein the chip stacked structure comprises:
• a first semiconductor chip comprising a first device layer and a first front side wiring structure on a front surface of the first device layer;
• a second semiconductor chip comprising a second device layer and a second front side wiring structure on a front surface of the second device layer, the second semiconductor chip being stacked on the first semiconductor chip;
• a through electrode penetrating at least a portion of the first semiconductor chip;
• and
• a through heat-dissipation film surrounding at least a portion of the through electrode,
• wherein the first front side wiring structure comprises:
• a first front side via layer comprising a first front side via;
• a first front side metal layer comprising a first front side wiring, the first front side metal layer being disposed on the first front side via layer;
• and
• a first front side heat-dissipation structure comprising a first portion surrounding a bottom surface and a side surface of the first front side via, and
• wherein the second front side wiring structure comprises:
• a second front side via layer comprising a second front side via;
• a second front side metal layer comprising a second front side wiring, the second front side metal layer being disposed on the second front side via layer;
• and
• a second front side heat-dissipation structure comprising a first portion surrounding a bottom surface and a side surface of the second front side via, and
• wherein each of the through heat-dissipation film, the first front side heat-dissipation structure, and the second front side heat-dissipation structure comprise a 2D material.