US 2026/0314394 A1 · PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A package structure includes a first semiconductor die, a first routing structure, a top die, a second routing structure, and a package substrate. The first semiconductor die includes a semiconductor substrate, a first transistor and a second transistor over the semiconductor substrate, a front side interconnect structure above first transistor and the second transistor, wherein the front side interconnect structure comprises a first inductor, wherein the first inductor is electrically coupled with source/drain regions of the first transistor and the second transistor, and a backside interconnect structure below the semiconductor substrate. The first routing structure is over and electrically connected to the first semiconductor die. The top die is over and electrically connected to the first routing structure. The second routing structure is below and electrically connected to the first semiconductor die. The package substrate is below and electrically connected to the second routing structure.

Claims20

Dependent claims

A package structure, comprising:

a first semiconductor die, comprising:
a semiconductor substrate;
a first transistor and a second transistor over the semiconductor substrate;
a front side interconnect structure above first transistor and the second transistor, wherein the front side interconnect structure comprises a first inductor, wherein the first inductor is electrically coupled with source/drain regions of the first transistor and the second transistor;
and
a backside interconnect structure below the semiconductor substrate;
a first routing structure over and electrically connected to the first semiconductor die;
a top die over and electrically connected to the first routing structure;
a second routing structure below and electrically connected to the first semiconductor die;
and
a package substrate below and electrically connected to the second routing structure.

8 more elements

A package structure, comprising:

a first semiconductor die, comprising:
a first transistor and a second transistor;
a first inductor, wherein a first side of the first inductor is electrically coupled with drain regions of the first transistor and the second transistor;
a first input terminal electrically coupled to a source region of the second transistor;
a first output terminal electrically coupled to a second side of the first inductor;
and
a first ground terminal electrically coupled to a source region of the first transistor;
a second semiconductor die stacking over the first semiconductor, comprising:
a third transistor and a fourth transistor;
a second inductor, wherein a first side of the second inductor is electrically coupled with drain regions of the third transistor and the fourth transistor;
a second input terminal electrically coupled to a source region of the fourth transistor and the first input terminal of the first semiconductor die;
a second output terminal electrically coupled to a second side of the second inductor and the first output terminal of the first semiconductor die;
and
a second ground terminal electrically coupled to a source region of the third transistor and the first ground terminal of the first semiconductor die;
a top die over and electrically connected to the second semiconductor die;
and
a package substrate below and electrically connected to the first semiconductor die.

14 more elements

Dependencies are inferred from the claim text.

Package structure and method for forming the same

Life of this patent

Package structure and method for forming the same

Life of this patent

Abstract

Claims20