Extended via connect for pixel array

A semiconductor structure, comprising:

• a substrate;
• a pixel circuit on the substrate and comprising a plurality of transistors;
• and
• an interconnect structure on the substrate, wherein the interconnect structure comprises a plurality of wires and a plurality of vias respectively grouped into a plurality of wire levels and a plurality of via levels that are alternatingly stacked, and wherein the interconnect structure further comprises an extended via;
• wherein the interconnect structure interconnects the transistors, and wherein the extended via partially forms the pixel circuit and has a height greater than a combined height of a wire level and a via level of the interconnect structure.

A method of forming an integrated chip, comprising:

• forming a dielectric structure overlying a first wire and a second wire;
• performing a first etch into the dielectric structure to form a first via opening and a second via opening respectively exposing the first and second wires;
• filling the first and second via openings respectively with a first dielectric plug and a second dielectric plug;
• performing a second etch into the dielectric structure to form a wire opening overlapping with the first via opening while the second via opening is masked, wherein the wire opening has a greater width than the first via opening;
• removing the first and second dielectric plugs;
• and
• filling the first and second via openings and the wire opening with conductive material to form a third wire, a via, and an extended via respectively in the wire opening, the first via opening, and the second via opening;
• wherein the extended via has a height greater than a combined height of the via and the third wire.