Method of forming a cap layer for sealing an air gap, and semiconductor device

A semiconductor device comprising:

• a semiconductor substrate having an upper surface and a recess recessed downwardly from the upper surface;
• an epitaxy region disposed in the recess;
• a contact plug disposed over the epitaxy region;
• a gate structure disposed on the upper surface of the semiconductor substrate and beside the contact plug;
• a gate spacer disposed on a sidewall of the gate structure;
• an air gap structure disposed on the semiconductor substrate in a manner such that the gate structure is separated by the contact plug by the air gap structure, the air gap structure having an air gap;
• and
• a cap layer disposed at an upper end of the air gap structure and sealing an opening of the air gap, the cap layer having a top portion and a bottom portion, a dimension of the top portion being greater than a dimension of the bottom portion,
• the air gap structure including a first contact etch stop layer (CESL) disposed on a sidewall of the gate spacer and a liner layer spaced apart from the first CESL by the air gap, upper ends of the first CESL and the liner layer being in direct contact with the cap layer, and having corners rounded off to accommodate the cap layer,
• an upper end of the gate spacer having a corner rounded off to form a receiving surface for accommodating the top portion of the cap layer, the receiving surface being inclined toward the semiconductor substrate from one side adjacent to the gate structure to an opposite side adjacent to the air gap.

A method of forming a cap layer for sealing an air gap, the method comprising:

• forming a line feature on a substrate, the line feature including a gate and a gate spacer formed on a sidewall of the gate;
• forming a first contact etch stop layer (CESL) on a sidewall of the gate spacer opposite to the gate;
• forming a sacrificial layer on a sidewall of the first CESL opposite to the gate spacer;
• forming a liner layer on a sidewall of the sacrificial layer opposite to the first CESL;
• removing the sacrificial layer to form an air gap which is bordered at the first CESL and the liner layer;
• etching back upper ends of the gate spacer, the first CESL and the liner layer to widen an opening of the air gap;
• and
• forming a cap layer to seal the opening of the air gap thus widened,
• the substrate including a first epitaxy region and a second epitaxy region spaced apart from each other, the line feature being formed on the substrate and beside the first epitaxy region and the second epitaxy region, wherein forming the first CESL includes:
• forming a CESL material over the gate, the gate spacer, the first epitaxy region and the second epitaxy region;
• forming an interlayer dielectric (ILD) layer over the CESL material;
• and
• planarizing the ILD layer where a portion of the CESL material is removed during planarizing the ILD layer to expose the gate and to form the first CESL on the sidewall of the gate spacer and over the first epitaxy region and the second epitaxy region,
• the method further comprising:
• replacing the gate of the line feature with a gate structure;
• and
• subsequent to replacing the gate of the line feature and prior to forming the sacrificial layer, removing the ILD layer and the first CESL over the first epitaxy region and the second epitaxy region to form a first contact hole and a second contact hole and to expose the first epitaxy region and the second epitaxy region from the first contact hole and the second contact hole, respectively.