Crystalline defect reduction in doped region

Abstract

The present disclosure generally relates to semiconductor processing for crystalline defects reduction in a doped region. In an example, an isolation structure is formed in a semiconductor substrate. The isolation structure extends from an upper surface of the semiconductor substrate into the semiconductor substrate. The isolation structure laterally surrounds at least in part an area of a bipolar junction transistor (BJT) in the semiconductor substrate. A dopant is implanted in a first region of the area. A second region of the area proximate a sidewall of the isolation structure is covered with a material blocking the dopant. A collector layer is formed on the area.

Dependencies are inferred from the claim text.