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US 2026/0314102 A1Published application
Deep trench isolation structure and methods for fabrication thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Yun YANG, Yu-Jen WANG
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Abstract
A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.
Claims20
A structure, comprising:
- a connection feature disposed in a semiconductor substrate, wherein a top surface of the connection feature is co-planar with a front surface of the semiconductor substrate;
- a deep trench isolation (DTI) structure formed in the semiconductor substrate, wherein a first surface of the DTI structure is coplanar with a back surface of the semiconductor substrate, and the DTI structure comprises:
- an isolation layer, wherein the isolation layer includes a sidewall portion in contact with the semiconductor substrate and a bottom portion in contact with the connection feature, wherein the isolation layer comprises a p-type semiconductor material;
- and
- a filling material disposed on the bottom portion and sidewall portion of the isolation layer;
- a plurality of pixel elements formed in and on the semiconductor substrate, wherein the DTI structure separates individual device elements;
- and
- an interconnection structure in electrical connection with the plurality of device elements and the connection feature.
5 more elements
A structure, comprising:
- a semiconductor substrate having a front surface and a back surface;
- a doped region of a first conductivity type disposed in the semiconductor substrate, the doped region having a first thickness;
- a connection feature extending from the front surface of the semiconductor substrate into the doped region, the connection feature comprising a first p-type semiconductor material;
- a deep trench isolation (DTI) structure extending into the doped region from the back surface, the DTI structure having a depth less than the first thickness of the doped region, the DTI structure comprising:
- an isolation layer comprising a second p-type semiconductor material, the isolation layer including a sidewall portion in contact with the doped region and a bottom portion in contact with the connection feature;
- and
- a filling material disposed on the bottom portion and the sidewall portion of the isolation layer;
- a plurality of pixel elements formed in and on the semiconductor substrate;
- and
- an interconnect structure in electrical communication with the plurality of pixel elements and the connection feature, the interconnect structure being configured to apply a bias voltage to the isolation layer through the connection feature.
7 more elements
A structure, comprising:
- a semiconductor substrate having a front surface and a back surface;
- a transistor region adjacent to the front surface of the semiconductor substrate;
- a doped region of a first conductivity type disposed between the transistor region and the back surface, the doped region having a first thickness;
- a connection feature disposed within the transistor region between the front surface and the doped region, the connection feature comprising a first p-type semiconductor material;
- a deep trench isolation (DTI) structure extending from the back surface through an entirety of the doped region and into the transistor region, the DTI structure having a depth greater than the first thickness of the doped region, the DTI structure comprising:
- an isolation layer comprising a second p-type semiconductor material, the isolation layer including a sidewall portion in contact with both the doped region and the transistor region, and a bottom portion in contact with the connection feature;
- and
- a filling material disposed on the bottom portion and the sidewall portion of the isolation layer;
- a plurality of pixel elements disposed in and on the semiconductor substrate;
- and
- an interconnect structure in electrical communication with the plurality of pixel elements and the connection feature.
8 more elements
Dependencies are inferred from the claim text.