Integrated chip and method of manufacturing the same

A method of forming an integrated chip, the method comprising:

• forming a first doped region in a semiconductor substrate along a first side of the semiconductor substrate, the semiconductor substrate including a bulk region having a first doping type, the first doped region having a second doping type different than the first doping type;
• etching the semiconductor substrate from a second side of the semiconductor substrate, opposite the first side, toward the first side to form a deep trench in the semiconductor substrate, wherein the deep trench is delimited by a first sidewall of the semiconductor substrate;
• depositing a dielectric layer in the deep trench and along the first sidewall of the semiconductor substrate;
• etching the dielectric layer and the semiconductor substrate from the second side of the semiconductor substrate toward the first side to form a grid trench in the semiconductor substrate and under the deep trench, wherein the grid trench is delimited by a second sidewall of the semiconductor substrate and a lower surface of the semiconductor substrate that extends from a top of the second sidewall to a bottom of the first sidewall of the semiconductor substrate;
• forming a second doped region in the semiconductor substrate along the second sidewall and the lower surface of the semiconductor substrate, the second doped region having the first doping type;
• and
• depositing a conductive layer in the deep trench along the dielectric layer and in the grid trench along the second sidewall and the lower surface of the semiconductor substrate so the conductive layer is coupled to the second doped region along the second sidewall and the lower surface of the semiconductor substrate.

A method of forming an integrated chip, the method comprising:

• forming a first doped region in a semiconductor substrate along a first side of the semiconductor substrate, the semiconductor substrate including a bulk region having a first doping type, the first doped region having a second doping type, different than the first doping type, the first doped region forming a first terminal of a single photon avalanche diode (SPAD);
• forming a deep trench isolation (DTI) structure extending from a second side of the semiconductor substrate toward the first side of the semiconductor substrate and laterally surrounding the SPAD, the DTI structure comprising a conductive core and a dielectric liner, wherein the dielectric liner is between a sidewall of the conductive core and a first sidewall of the semiconductor substrate;
• forming a conductive grid structure under the DTI structure and coupled to the conductive core, wherein the conductive grid structure has a sidewall and an upper surface, the upper surface extending from a top of the sidewall of the conductive grid structure to a bottom of the sidewall of the conductive core of the DTI structure;
• and
• forming a second terminal of the SPAD along the second side of the semiconductor substrate, wherein the second terminal has the first doping type and is coupled to the conductive grid structure along the upper surface of the conductive grid structure and the sidewall of the conductive grid structure.