Semiconductor device

A method for manufacturing a semiconductor device, comprising:

• forming a substrate that includes a PMOS region and a NMOS region defined therein;
• forming a first pattern extending in a first direction on the PMOS region of the substrate, and forming a second pattern extending in the first direction on the NMOS region of the substrate;
• forming a first etch stop layer including an insulating material on the first pattern, and forming a second etch stop layer including an insulating material on the second pattern, wherein the first and second etch stop layers have a same vertical level above the substrate;
• forming a plurality of first nanosheets including silicon germanium (SiGe) on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction;
• forming a first source/drain region on the first pattern, wherein the first source/drain region is in contact with the first etch stop layer;
• forming a plurality of second nanosheets on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction;
• and
• forming a first gate electrode extending in a second direction that differs from the first direction on the first etch stop layer, wherein the first gate electrode surrounds the plurality of first nanosheets, and a portion of the first gate electrode is formed between the first etch stop layer and a lowermost first nanosheet in the vertical direction.

A method for manufacturing a semiconductor device, comprising:

• forming a substrate that includes a PMOS region and a NMOS region defined therein;
• forming a first pattern extending in a first direction on the PMOS region of the substrate, and forming a second pattern extending in the first direction on the NMOS region of the substrate;
• forming a first etch stop layer including an insulating material on the first pattern, and forming a second etch stop layer including an insulating material on the second pattern, wherein the first and second etch stop layers have a same vertical level above the substrate;
• forming a plurality of first nanosheets including silicon germanium (SiGe) on the first etch stop layer, wherein the plurality of first nanosheets are stacked and spaced apart from each other in a vertical direction;
• forming a first source/drain region on the first pattern, wherein a bottom surface of the first source/drain region is in contact with the first etch stop layer;
• forming a plurality of second nanosheets including silicon (Si) on the second etch stop layer, wherein the plurality of second nanosheets are stacked and spaced apart from each other in the vertical direction, and vertical levels above the substrate of the plurality of second nanosheets differ from vertical levels above the substrate of the plurality of first nanosheets;
• forming a second source/drain region on the second pattern, wherein a bottom surface of the second source/drain region is in contact with the second etch stop layer;
• forming a first gate electrode extending in a second direction that differs from the first direction on the first etch stop layer, wherein the first gate electrode surrounds the plurality of first nanosheets, and a portion of the first gate electrode is formed between the first etch stop layer and a lowermost first nanosheet in the vertical direction;
• and
• forming a second gate electrode extending in the second direction on the second etch stop layer, wherein the second gate electrode surrounds the plurality of second nanosheets.