Semiconductor device and methods of forming the same

A semiconductor device, comprising:

• a substrate;
• a channel region disposed over the substrate;
• a gate electrode having a longitudinal axis in a first direction and over the channel region, wherein the gate electrode comprises a first sidewall extending along the first direction and a second sidewall extending along a second direction perpendicular to the first direction, wherein the first sidewall comprises a first major surface and first protrusions protruding over the first major surface, and the second sidewall comprises a second major surface and second protrusions protruding over the second major surface, wherein the first major surface and the second major surface are flat surfaces;
• epitaxial source/drain features interposing the channel region in the second direction;
• an insulating layer disposed over the epitaxial source/drain features;
• and
• a contact extending through the insulating layer to be electrically coupled to the epitaxial source/drain features, wherein an electrical conductivity of the contact is greater than an electrical conductivity of the epitaxial source/drain features.

A method for forming a semiconductor device, the method comprising:

• forming a semiconductor strip over a substrate, wherein the semiconductor strip comprises first semiconductor layers and second semiconductor layers stacked alternatingly;
• forming a dummy gate layer over the substrate and crossing over the semiconductor strip, wherein the forming the dummy gate layer comprises:
• performing a first cycle multiple times and a second cycle at least one time, wherein the first cycle comprises a first deposition step and a first etch step, and the second cycle comprises a second deposition step and has no etch step, wherein the first deposition step and the second deposition step is operated at a first temperature;
• and
• performing a third cycle multiple times and a fourth cycle at least one time, wherein the third cycle comprises a third deposition step and a second etch step, and the second cycle comprises a fourth deposition step and has no etch step, wherein the third deposition step and the fourth deposition step is operated at a second temperature greater than the first temperature;
• forming gate spacers over opposite sidewalls of the dummy gate layer in a first direction;
• etching the first semiconductor layers and the second semiconductor layers along the gate spacers to form first nanostructures and second nanostructures, respectively;
• forming epitaxial source/drain features interposing the first nanostructures, wherein each of the epitaxial source/drain features comprises two layers that contain a same semiconductor material with different concentrations;
• replacing the second nanostructures and the dummy gate layer with a gate electrode;
• and
• forming an interlayer dielectric layer over the gate electrode and the epitaxial source/drain features, wherein the interlayer dielectric layer has a height thinner than a total height of the gate electrode.