Backside contact to devices with wide source/drain regions

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a plurality of semiconductor nanoribbons extending in a first direction from a source or drain region;
• a gate structure extending in a second direction over the plurality of semiconductor nanoribbons;
• and
• a backside contact extending through a bottom surface of the source or drain region;
• wherein the source or drain region has a width along the first direction that is greater than 50 nm and comprises a first epitaxial region on at least a portion of the plurality of semiconductor nanoribbons and a second epitaxial region on the first epitaxial region, each of the first epitaxial region and second epitaxial region comprising n-type or p-type dopant.

An integrated circuit comprising:

• a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor region;
• and
• a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region, and a second gate structure extending in a second direction over the second semiconductor region, the second source or drain region having a width that is at least twice as large as a width of the first source or drain region along the first direction;
• wherein the second source or drain region comprises a first epitaxial region on at least a portion of the second semiconductor region and a second epitaxial region on the first epitaxial region, each of the first epitaxial region and second epitaxial region comprising n-type or p-type dopant.