Replacement sidewall spacers

A semiconductor device, comprising:

• a gate structure;
• a composite spacer structure on a sidewall of the gate structure, the composite spacer structure including a first spacer layer and a second spacer layer;
• the first spacer layer being adjacent to the gate structure and having a first spacer height extending from a lower surface of the first spacer layer to an upper surface of the first spacer layer;
• the second spacer layer being adjacent to the first spacer layer and having a second spacer height extending from a lower surface of the second spacer layer to an upper surface of the second spacer layer, the second spacer height being greater than the first spacer height;
• the first spacer layer being formed from a first dielectric material and the second spacer layer being formed from a second dielectric material different from the first dielectric material;
• and
• an interlayer dielectric adjacent to the second spacer layer, wherein a portion of the second spacer layer above the upper surface of the first spacer layer separates the gate structure from the interlayer dielectric.

A semiconductor device, comprising:

• a fin structure including one or more semiconductor layers;
• a gate structure over the fin structure, the gate structure including a gate dielectric layer on the one or more semiconductor layers and a gate electrode over the gate dielectric layer, the gate structure wrapping around the one or more semiconductor layers;
• a first spacer portion between the gate structure and an interlayer dielectric at a lower region of the gate structure, the first spacer portion having a first spacer width;
• and
• a second spacer portion between the gate structure and the interlayer dielectric, the second spacer portion being adjacent to the first spacer portion at the lower region of the gate structure and extending along an upper region of the gate structure, the second spacer portion having a second spacer width at the lower region of the gate structure;
• wherein the first spacer width is less than the second spacer width;
• and
• wherein a gate width of the gate structure at the upper region is greater than a gate width of the gate structure at the lower region.