Selective high-k formation in gate-last process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYasutoshi Okuno, Fu-Ting Yen, Teng-Chun Tsai, Ziwei Fang
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Abstract
A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.
Claims20
A device comprising:
- a substrate;
- a semiconductor region over the substrate;
- a gate spacer over the semiconductor region;
- a gate stack wrapping around the semiconductor region, wherein the gate stack comprises:
- a dielectric interfacial layer over the semiconductor region, wherein the dielectric interfacial layer is laterally spaced apart from the gate spacer;
- a high-k gate dielectric spaced apart from the semiconductor region by the dielectric interfacial layer, wherein the high-k gate dielectric comprises a horizontal portion overlapping the dielectric interfacial layer;
- and
- a conductive gate electrode over the high-k gate dielectric, wherein the conductive gate electrode comprises a sub-layer comprising a bottom portion, and sidewall portions connected to opposite ends of the bottom portion, and wherein the conductive gate electrode comprises a Ti-based material;
- a source/drain region on a side of the gate stack;
- a source/drain contact over and connected to the source/drain region;
- a contact etch stop layer (CESL) over the source/drain region;
- and
- an inter-layer dielectric (ILD) over the CESL, wherein the source/drain contact is encircled by the CESL and the ILD.
A device comprising:
- a semiconductor region;
- a first gate spacer and a second gate spacer on opposing sides of the semiconductor region;
- a spacing region on a sidewall of the first gate spacer;
- a dielectric interfacial layer surrounding the semiconductor region;
- a high-k gate dielectric over the dielectric interfacial layer, wherein the high-k gate dielectric is between the first gate spacer and the second gate spacer, and wherein in a cross-sectional view of the device, the high-k gate dielectric comprises a planar portion that is over a top surface of the semiconductor region;
- a metal gate electrode overlying the high-k gate dielectric, wherein the metal gate electrode comprises a work-function layer, and wherein in the cross-sectional view, a portion of the work-function layer has a U-shape;
- a source/drain region on a side of the first gate spacer;
- a contact etch stop layer (CESL) over the source/drain region;
- an interlayer dielectric (ILD) over the CESL, wherein the CESL and the ILD comprise different dielectric materials;
- and
- a source/drain contact surrounded by the ILD and the CESL.
A device comprising:
- a substrate;
- isolation regions extending into the substrate;
- a semiconductor channel structure between opposing portions of the isolation regions, wherein the semiconductor channel structure is higher than the isolation regions;
- a gate spacer over the semiconductor channel structure;
- a silicon oxide layer wrapping around the semiconductor channel structure;
- a high-k gate dielectric contacting the silicon oxide layer, wherein at least one of the silicon oxide layer and the high-k gate dielectric is spaced apart from the gate spacer;
- and
- conductive layers over the high-k gate dielectric.
Dependencies are inferred from the claim text.