Integrated circuit structure and method for forming the same
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsShih-Yen LIN, Che-Jia CHANG
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Abstract
A method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.
Claims20
An integrated circuit, comprising:
- a substrate;
- a transistor over the substrate;
- a dielectric layer over the transistor;
- and
- an interconnect structure in the dielectric layer and electrically connected to the transistor, wherein the interconnect structure comprises:
- a first metal-free 2-D material layer;
- a first metal-containing 2-D material layer;
- and
- a first metal layer over the first metal-containing 2-D material layer.
An integrated circuit, comprising:
- a substrate;
- a transistor over the substrate;
- a dielectric layer over the transistor;
- and
- an interconnect structure in the dielectric layer and electrically connected to the transistor, wherein the interconnect structure comprises:
- a first 2-D material layer;
- a second 2-D material layer over the first 2-D material layer, wherein a bottom surface of the second 2-D material layer is higher than a bottom surface of the first 2-D material layer, and wherein the first 2-D material layer interfaces with a top surface of a channel layer of the transistor and the bottom surface of the second 2-D material layer;
- and
- a metal layer over the second 2-D material layer.
An integrated circuit, comprising:
- a substrate;
- a transistor over the substrate;
- a dielectric layer over the transistor;
- and
- an interconnect structure in the dielectric layer and electrically connected to the transistor, wherein the interconnect structure comprises:
- a first metal-free 2-D material layer;
- a first metal-containing 2-D material layer;
- and
- a first metal layer over the first metal-containing 2-D material layer, wherein the first metal layer has a dual damascene structure comprising a via portion and a metal line portion over the via portion, the metal line portion being wider than the via portion, and the first metal-containing 2-D material layer has a horizontal portion interfacing with a bottom surface of the metal line portion.
Dependencies are inferred from the claim text.