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US 2026/0313981 A1Published application
Transistor Including Dielectric Barrier And Manufacturing Method Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chih-Hao WANG, Chien Ning YAO, Kuo-Cheng CHIANG
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Abstract
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by dielectric barriers. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.
Claims20
An integrated circuit, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first channel region including first and second semiconductor nanostructures vertically separated from each other;
- an inner spacer between the first and second semiconductor nanostructures;
- and
- a first source/drain region above the semiconductor substrate and coupled to the first channel region;
- and
- a dielectric barrier of a same dielectric material as the inner spacer over the semiconductor substrate and electrically isolating the first source region from the semiconductor substrate.
5 more elements
A device, comprising:
- a semiconductor substrate;
- a first semiconductor fin over the semiconductor substrate;
- a second semiconductor fin over the semiconductor substrate;
- a first trench in the first semiconductor fin;
- a second trench in the second semiconductor fin;
- a dielectric barrier on the semiconductor substrate in a bottom of the first trench;
- and
- a first transistor including a first channel region and a first source/drain region on the dielectric barrier in the first trench, wherein the dielectric barrier electrically isolates the first source region from the semiconductor substrate;
- a second transistor including a second channel region and a second source/drain region in the second trench and in contact with the semiconductor substrate at a bottom of the second trench, wherein the first source/drain region and the second source/drain region have a same first conductivity type.
6 more elements
A device, comprising:
- a semiconductor substrate;
- a first semiconductor fin over the semiconductor substrate;
- a second semiconductor fin over the semiconductor substrate;
- a first trench in the first semiconductor fin;
- a second trench in the second semiconductor fin;
- a first dielectric barrier on the semiconductor substrate in a bottom of the first trench;
- a first transistor including a pair of stacked first channels in the first fin above the semiconductor substrate adjacent to the first trench;
- a second transistor including a pair of stacked second channels in the second semiconductor fin;
- a first inner spacer between the first channels, wherein the first inner spacer and the first dielectric barrier are a same dielectric material;
- a first source/drain region of the first transistor in the first trench above and in contact with the first dielectric barrier and coupled to the first and second channels, wherein the dielectric barrier electrically isolates the first source/drain region from the semiconductor substrate;
- and
- a second source/drain region of the second transistor in the second trench in contact with semiconductor substrate.
9 more elements
Dependencies are inferred from the claim text.