Microelectronic devices, and related methods and memory devices

A method of forming a microelectronic device, comprising:

• forming a first microelectronic device structure comprising one or more of control logic circuitry and power management circuitry;
• forming a second microelectronic device structure comprising:
• a semiconductor material overlying a base structure;
• a stack structure overlying the semiconductor material and comprising conductive material vertically alternating with insulative material;
• and
• a cell pillar structure vertically extending through the stack structure and into the semiconductor material, the cell pillar structure comprising a channel material horizontally interposed between an outer material stack and a dielectric fill material;
• bonding the second microelectronic device structure to the first microelectronic device structure to form an assembly;
• after forming the assembly, removing the base structure, the semiconductor material, and a portion of the cell pillar structure to partially expose the channel material of the cell pillar structure;
• forming metal material in physical contact with at least one exposed portion of the channel material of the cell pillar structure and having a work function within a range of from about 3.6 eV to about 4.7 eV;
• and
• forming additional metal material in physical contact with at least one additional exposed portion of the channel material of the cell pillar structure and having an additional work function within a range of from about 4.4 eV to about 5.3 eV.

A memory device, comprising:

• a memory array region comprising:
• a stack structure comprising a vertically alternating sequence of conductive material and insulative material;
• an active body structure vertically offset from the stack structure and comprising:
• a first metal material having a first work function less than or equal to about 4.7 eV;
• and
• a second metal material having a second work function greater than or equal to about 4.4 eV;
• a cell pillar structure comprising semiconductor material extending through the stack structure and contacting the active body structure to form:
• a first Schottky contact at an interface between the semiconductor material and the first metal material;
• and
• a second Schottky contact at an additional interface between the semiconductor material and the second metal material;
• and
• a peripheral circuitry region vertically offset from and horizontally overlapping the memory array region, the peripheral circuitry region comprising control logic devices in electrical communication with the cell pillar structure.