Semiconductor device with aligned channel structures and gate contact structures

A semiconductor device, comprising:

• gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of a substrate;
• interlayer insulating layers alternately stacked with the gate electrodes;
• channel structures extending into the gate electrodes in the first direction, wherein each of the channel structures includes a channel layer;
• gate contact plugs extending into the gate electrodes in the first direction, wherein the each of the gate contact plugs are electrically connected to respective ones of the gate electrodes;
• common source layers in contact with the channel layers on the channel structures;
• a cell region insulating layer below the channel structures and the gate contact plugs;
• and
• bitlines electrically connected to respective ones of the channel structures in the cell region insulating layer,
• wherein each of the channel structures includes first to third channel portions stacked in order from a lower portion,
• wherein at least the third channel portion includes a region having an inclined side surface, and a width of the region decreases toward the substrate, and
• wherein lower ends of the channel structures and lower ends of the gate contact plugs are in an insulating structure including a lowermost interlayer insulating layer among the interlayer insulating layers and the cell region insulating layer.

A data storage system, comprising:

• a semiconductor storage device including a first semiconductor structure including circuit elements, a second semiconductor structure on the first semiconductor structure, and an input/output pad electrically connected to the circuit elements;
• and
• a controller electrically connected to the semiconductor storage device through the input/output pads,
• wherein the second semiconductor structure includes
• gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the first semiconductor structure;
• interlayer insulating layers alternately stacked with the gate electrodes;
• channel structures extending into the gate electrodes in the first direction, wherein each of the channel structures includes a channel layer;
• gate contact plugs extending into the gate electrodes in the first direction and electrically connected to respective ones of the gate electrodes;
• a common source layer in contact with the channel layer on the channel structures;
• a cell region insulating layer below the channel structures and the gate contact plugs;
• and
• bitlines electrically connected to respective ones of the channel structures in the cell region insulating layer,
• wherein each of the channel structures includes first, second, and third channel portions stacked in order from a lower portion,
• wherein each of the gate contact plugs includes first, second, and third contact portions stacked in order from a lower portion, and
• wherein each of the third channel portion and the third contact portion includes a region having an inclined side surface and a width of each of the regions decreases toward the upper surface of the first semiconductor structure.