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US 2026/0313891 A1Published application
Flash memory with improved gate structure and a method of creating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSheng-Chieh CHEN, Ming Chyi LIU, Shih-Chang LIU
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Abstract
Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
Claims20
A method, comprising:
- forming a memory gate on a substrate;
- forming a selection gate on the substrate;
- forming a gate dielectric layer between the memory gate and the selection gate;
- forming a protective layer on the gate dielectric layer and between the memory gate and the selection gate;
- removing upper portions of the protective layer and the gate dielectric layer using a chemical-mechanical planarization process to form a protective cap, such that a surface of the memory gate, a surface of the selection gate, and a surface of the protective cap are coplanar with each other;
- forming a first contact layer on the coplanar surface of the memory gate and a second contact layer on the coplanar surface of the selection gate;
- forming an interlayer dielectric over the memory gate, the selection gate, and the protective cap;
- and
- forming a first conductive via extending through the interlayer dielectric and electrically coupled to the first contact layer, and a second conductive via extending through the interlayer dielectric and electrically coupled to the second contact layer.
6 more elements
A method, comprising:
- forming a memory gate on a substrate;
- forming a selection gate on the substrate;
- forming a gate dielectric layer between the memory gate and the selection gate;
- forming a cavity having sidewalls formed by the memory gate and the selection gate, and a base formed by the gate dielectric layer;
- forming a protective cap in the cavity;
- depositing a conductive material on the memory gate and the selection gate, wherein the protective cap prevents the conductive material from being formed in the cavity;
- and
- annealing the conductive material to form silicide layers on the memory gate and the selection gate.
5 more elements
A method, comprising:
- forming a memory gate on a substrate;
- forming a selection gate on the substrate;
- forming a gate dielectric layer between the memory gate and the selection gate;
- forming a protective layer on the gate dielectric layer and between the memory gate and the selection gate;
- removing upper portions of the protective layer to form a protective cap such that a surface of the memory gate, a surface of the selection gate, and a surface of the protective cap are coplanar with each other;
- and
- after the removing of the upper portions of the protective layer, forming a first spacer laterally to the memory gate and a second spacer laterally to the selection gate, and forming a source region and a drain region in the substrate, wherein the protective cap covers an upper surface of the gate dielectric layer during the forming of the first spacer, the second spacer, the source region, and the drain region.
4 more elements
Dependencies are inferred from the claim text.