Method for manufacturing semiconductor memory device including a bit line mask pattern

A method for manufacturing a semiconductor memory device, the method comprising forming, on a substrate, a PMOS region, a first NMOS region, and a second NMOS region that are spaced apart from each other in a first direction, the PMOS region being between the first NMOS region and the second NMOS region,

• wherein forming the PMOS region includes:
• performing a first patterning process to form, on the substrate, a first sensing bit line and a second sensing bit line using a first mask pattern, wherein the first sensing bit line and the second sensing bit line extend in the first direction and are spaced apart from each other in a second direction intersecting the first direction;
• and
• forming a drain pattern spaced apart from the second sensing bit line in the second direction, the first sensing bit line being between the drain pattern and the second sensing bit line,
• wherein the first mask pattern includes a first sensing bit line mask pattern corresponding to the first sensing bit line, and
• wherein the first sensing bit line mask pattern includes:
• a first portion extending in the first direction;
• a second portion extending in the second direction and spaced apart from the first portion in the first direction;
• and
• a third portion between the first portion and the second portion,
• wherein each of the first portion, the second portion, and the third portion includes a first sidewall, a second sidewall, and a third sidewall, and
• wherein the third sidewall is offset from the first sidewall and the second sidewall in the second direction.

A method for manufacturing a semiconductor memory device, the method comprising forming a PMOS region, a first NMOS region, and a second NMOS region, wherein the first NMOS region and the second NMOS region are spaced apart from each other in a first direction, and the PMOS region is between the first NMOS region and the second NMOS region,

• wherein the forming of the first NMOS region includes:
• performing a first patterning process to form a first bit line and a second bit line using a first mask pattern, wherein the first bit line and the second bit line extend in the first direction on a substrate and are spaced apart from each other in a second direction intersecting the first direction;
• forming a cancellation region adjacent to the PMOS region, wherein the cancellation region includes a cancellation gate electrode extending in the second direction;
• forming a first interlayer insulating layer on the first and second bit lines;
• forming a first source pattern between the first bit line and the second bit line;
• forming first drain patterns between the first bit line and the cancellation gate electrode and between the second bit line and the cancellation gate electrode;
• and
• forming a wiring layer on the first interlayer insulating layer,
• wherein the first mask pattern includes a first bit line mask pattern corresponding to the first bit line and a second bit line mask pattern corresponding to the second bit line,
• wherein the first bit line mask pattern includes a first protrusion pattern protruding from a first end portion of the first bit line mask pattern toward the second bit line mask pattern, and
• wherein the second bit line mask pattern includes a second protrusion pattern protruding from a second end portion of the second bit line mask pattern toward the first bit line mask pattern.