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AssigneesUniversitat Autonoma De Barcelona, Consejo Superior De Investigaciones Cientificas (Csic)
InventorsJosep Maria Margarit Taulé, Javier Cuenca Michans, Lluís Terés Terés, Francisco Serra Graells
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Delta-sigma device comprising transducers (2) and delta-sigma modulators (3) wherein the transducers (2) comprise: a sensing stage (100) that detect a property of the environment (106) and an interfacing stage (101); and the delta-sigma modulators (3) comprise: an input stage connected to the interfacing stages (101), comprising the input stage two subtracting stages (113, 114), for receiving an unfiltered intramodulator feedback signal (109) and a low-pass-filtered intramodulator feedback signal (110), and subtracting them from a sum of one or more of the input transduced signals (108) to obtain a delta error signal (111), a feedforward low-pass filtering stage (102); an analog-to-digital encoder (104), that converts the filtered delta error signal into a digital output signal dout(t) (112), an unfiltered intramodulator feedback path, that converts dout(t) (112) into the unfiltered intramodulator feedback signal (109), and a low-pass-filtered intramodulator feedback path, that converts dout(t) (112) into the low-pass-filtered intramodulator feedback signal (110).
—A delta-sigma device characterized in that it comprises one or more transducers (2) and one or more delta-sigma modulators (3) wherein each of the transducers (2) comprises:
—The device of claim 1, wherein the background signals are a drift and/or an offset.
—The device of claim 1, wherein each transducer (2) is connected to a single delta-sigma modulator (3) or to more than one delta-sigma modulator (3).
—The device of claim 1, wherein it comprises one or more transducers (2) and two or more delta-sigma modulators (3), and wherein the device additionally comprises a plurality of unfiltered intermodulator feedback paths that comprise one or more third digital-to-analog converters (305), connected to dout(t) (112) of each delta-sigma modulator (3) and configured to convert dout(t) into a plurality of unfiltered intermodulator feedback signals (116), and wherein the device comprises an additional subtracting stage (117) before the feedforward low-pass filtering stage (102) configured to receive the unfiltered intermodulator feedback signals (116) of each one of the other delta-sigma modulators (3) to subtract them from the delta error signal (111).
—The device of claim 1, wherein the feedforward low-pass filtering stage (102) or the feedback low-pass filtering stage (103) comprise one or more leaky or non-leaky integrator stages, each integrator stage being configured to integrate a respective input signal.
—The device of claim 5, wherein one or more of the leaky or non-leaky integrator stages of the feedforward low-pass filtering stage (102) is a small-signal circuit equivalent of the dynamic electrical response of the transducer (2) under small-signal excitation.
—The device of claim 1, wherein the analog-to-digital encoder (104) of the delta-sigma modulators (3) comprises a one-bit synchronous or asynchronous quantizer or a three-level asynchronous or synchronous quantizer.
—The device of claim 1, wherein the analog-to-digital encoder (104) of the delta-sigma modulators (3) comprises a one-bit asynchronous quantizer and a pulse generator that convert the filtered delta error signal into a digital pulsing signal dout(t) (112).
—The device of claim 8, wherein the feedback low-pass filtering stage (103) additionally comprises a FIR (Finite Impulse Response) or IIR (Infinite Impulse Response) digital low-pass filter.
—The device of claim 9, wherein the feedback low-pass filtering stage (103) additionally comprises an asynchronous counter stage, with a predetermined clock period, connected between dout(t) and the digital low-pass filter, and configured to integrate the number of asynchorous dout(t) pulses throughout the clock period.
—The device of claim 1, wherein the analog-to-digital encoders (104) of the delta-sigma modulators (3) comprise a three-level asynchronous quantizer and a three-level bipolar pulse generator that convert the filtered delta error signal into a digital bipolar pulsing signal dout(t) (112), wherein the three-level asynchronous quantizer is configured to send a signal to the three-level bipolar pulse generator to generate three different digital signals each one corresponding to a predetermined range of values of the filtered delta error signal received.
—The device of claim 4, wherein the sensing stage (100) and the interfacing stage (101) of the transducers (2) and a leaky integrator stage of the feedforward low-pass filtering stage (102) are three-electrode cells operating as a potentiostatic-amperometric sensor, and wherein the unfiltered intramodulator feedback signals (109) and the low-pass-filtered intramodulator feedback signals (110) are subtracted in current-mode from the amplified input signals, and the unfiltered intermodulator feedback signals (116) are subtracted in current-mode from the inputs of any of the integrator stages comprised in the feedforward low-pass filtering stage, wherein the feedforward low-pass filtering stage is connected to the analog-to-digital encoder (104), which is connected to the unfiltered intramodulator feedback path and the low-pass filtered intramodulator feedback path.
—The device of claim 12, further comprising a second current source (911) in the unfiltered intramodulator feedback path configured to perform digital-to-analog conversion controlled by dout(t), and a first current source comprised of a metal-oxide-semiconductor (MOS) transistor (901) configured to perform amplification and digital-to-analog conversion of the low-pass intramodulator feedback path controlled by dout(t).
—The device of claim 13, wherein the metal-oxide-semiconductor (MOS) transistor is operated with a selectable drain-source voltage biased to have a null drain-source voltage when the output of dout(t) is zero or to a null source-bulk voltages, and, when the output of dout(t) is not zero, a non-zero very low drain-source voltage is selected, being proportional to dout(t).
—The device of claim 4, wherein the sensing stage (100) comprises a FET sensor, and the interfacing stage (101) performs capacitive amplification through the passivation capacitance of the FET sensor and a feedback capacitance, and wherein the low-pass-filtered intramodulator feedback signals (110), and the unfiltered intramodulator feedback signals (109), the unfiltered intermodulator feedback signals (116) are subtracted in current-mode from the amplified input transduced signals (108).