Phase-Locked Loop Circuit
AssigneeNovatek Microelectronics Corp.
InventorsYi-Wen Hung, Bing-Syun Wu, Tung-Cheng Hsin
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Abstract
A phase-locked loop circuit includes a digital control oscillator, configured to generate an output clock signal according to at least one control code generated using at least one phase error signal; and a phase detector, configured to generate the at least one phase error signal according to a rising edge difference and a rising edge lead-lag relation between a rising edge of a first clock signal and a corresponding edge of an edge alignment corrected feedback signal; wherein the edge alignment corrected feedback signal is generated based on the output clock signal.
Claims9
A phase-locked loop (PLL) circuit, comprising:
- a digital control oscillator, configured to generate an output clock signal according to at least one control code generated using at least one phase error signal;
- and
- a phase detector, configured to generate the at least one phase error signal according to a rising edge difference and a rising edge lead-lag relation between a rising edge of a first clock signal and a corresponding edge of an edge alignment corrected feedback signal;
- wherein the edge alignment corrected feedback signal is generated based on the output clock signal.
A phase detector, for a phase-locked loop (PLL) circuit, comprising:
- a counter, configured to generate an edge alignment corrected feedback signal according to an output clock signal of the PLL circuit;
- an edge sampler, configured to generate a first sampled signal corresponding to a rising edge of a first clock signal of the PLL circuit and a second sampled signal corresponding to a rising edge lead-lag relation between the rising edge of the first clock signal and a corresponding edge of the edge alignment corrected feedback signal according to the first clock signal and the output clock signal;
- and
- a phase quantization circuit, coupled to the counter and the edge sampler, configured to generate at least one phase error signal according to the first sampled signal, the second sampled signal and the edge alignment corrected feedback signal.
Dependencies are inferred from the claim text.