US 2026/0312592 A1 · LOCK DETECTOR INCLUDING DIGITAL CALIBRATION

Abstract

A lock detector including a first digital-to-time converter (DTC) that delays a reference clock based on a first digital code to provide a first delayed clock; a second DTC that delays a target clock based on a second digital code to provide a second delayed clock; a phase difference detection circuit that obtains an error signal indicating a phase relationship between the first delayed clock and the second delayed clock; a calibration circuit that calibrates the first digital code to reduce a phase difference between the first delayed clock and the second delayed clock based on the error signal; and a lock detection circuit that provides a lock detection signal indicating whether the first delayed clock and the second delayed clock are within a set lock detection range.

Claims20

Dependent claims

A lock detector comprising:

a first digital-to-time converter (DTC) configured to delay a reference clock based on a first digital code to provide a first delayed clock;
a second DTC configured to delay a target clock based on a second digital code to provide a second delayed clock;
a phase difference detection circuit configured to obtain an error signal indicating a phase relationship between the first delayed clock and the second delayed clock;
a calibration circuit configured to calibrate the first digital code to reduce a phase difference between the first delayed clock and the second delayed clock based on the error signal;
and
a lock detection circuit configured to provide a lock detection signal indicating whether the first delayed clock and the second delayed clock are within a set lock detection range.

3 more elements

A radio-frequency (RF) chip comprising:

a phase locked loop (PLL) circuit configured to detect a phase difference between a reference clock and a target clock, and adjust a frequency of the target clock to reduce the phase difference;
and
a lock detector configured to provide a first delayed clock by delaying the reference clock based on a first digital code, provide a second delayed clock by delaying the target clock based on a second digital code, provide an error signal indicating a phase relationship between the first delayed clock and the second delayed clock, calibrate the first digital code to reduce a phase difference between the first delayed clock and the second delayed clock based on the error signal, and provide a lock detection signal indicating whether the first delayed clock and the second delayed clock are within a set lock detection range.

Dependencies are inferred from the claim text.

Lock detector including digital calibration

Life of this patent

Lock detector including digital calibration

Life of this patent

Abstract

Claims20