Memory device with a precharge circuit
OwnerAyumu Yamada, Ryota Watanabeinventors
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Abstract
A semiconductor device may include a memory array having a bit line and a memory cell coupled to the bit line. The semiconductor device further includes a sensing circuit to sense data from the memory cell. The semiconductor device further including a pre-charge circuit having an asymmetric clocked inverter having an input terminal, an output terminal, and at least one enable terminal. The input terminal is connected to the bit line. The output terminal is connected to the bit line. In response to receiving an enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit line to a pre-charge voltage. The pre-charge voltage is higher than a threshold voltage of a sensing circuit and lower than the supply voltage.
Claims20
A semiconductor device comprising:
- a memory array having a bit line and a memory cell coupled to the bit line;
- a sensing circuit configured to sense data from the memory cell;
- and
- a pre-charge circuit comprising an asymmetric clocked inverter having an input terminal, an output terminal, and at least one enable terminal, wherein:
- the input terminal is connected to the bit line,
- the output terminal is connected to the bit line, and
- in response to receiving an enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit line to a pre-charge voltage, wherein the pre-charge voltage is higher than a threshold voltage of the sensing circuit and lower than the supply voltage.
A semiconductor device comprising:
- a memory array having a bit line and a memory cell coupled to the bit line;
- a pre-charge circuit comprising a first terminal, a second terminal, and at least one enable terminal, wherein the first terminal is connected to the bit line, and wherein in response to receiving apre-charge enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit line to a pre-charge voltage;
- and
- a voltage detector circuit comprising a first terminal and a second terminal, wherein the first terminal of the voltage detector is connected to the bit line, wherein the second terminal of the voltage detector is connected to the second terminal of the pre-charge circuit, wherein the voltage detector is configured to sense a bit line voltage of the bit line and provide a bit line feedback signal to the pre-charge circuit based on the sensed bit line voltage, and wherein the pre-charge circuit is configured to alter pre-charging of the bit line based on the bit line feedback signal.
A method of performing a read operation on a memory device, the method comprising:
- selecting a bit line of a memory array of the memory device, and the memory device having a memory cell coupled to the bit line;
- enabling a pre-charge circuit to pre-charge the bit line to a pre-charge voltage, wherein the pre-charge circuit comprises an asymmetric clocked inverter having an input terminal, an output terminal, and at least one enable terminal, wherein:
- the input terminal is connected to the bit line,
- the output terminal is connected to the bit line, and
- in response to receiving an enable signal on the at least one enable terminal, the pre-charge circuit pre-charges the bit line to the pre-charge voltage;
- and
- enabling, after pre-charging of the bit line, a sensing circuit to perform a read operation on the memory cell connected to the bit line.
Dependencies are inferred from the claim text.