In-memory computation device having an analog compensation and method

A method for controlling an in-memory computation (IMC) device comprising a computation memory array including a plurality of memory cells coupled to a bit line and a plurality of word lines and each storing a respective computational weight, wherein the method comprises:

• receiving a plurality of input values and providing, in response to and as a function of the plurality of input values, a plurality of activation signals to the plurality of word lines;
• providing a corrected bias voltage to the bit line;
• providing, as a function of a bit line current, an output signal indicative of a charge flowing in the bit line;
• wherein each memory cell is configured to be traversed by a respective cell current that is a function of the corrected bias voltage, the activation signal received from the respective word line and the respective computational weight;
• wherein the bit line current is a function of a sum of the cell currents of the memory cells coupled to the bit line;
• and
• wherein the corrected bias voltage is generated a function of a common bias signal and a calibration factor, wherein the calibration factor is determined during a calibration step of the IMC device and is representative of an error between an actual computational result and an ideal computational result of the calibration step.

A method for calibrating an in-memory computation (IMC) device comprising a computation memory array including a plurality of memory cells coupled to a bit line and a plurality of word lines and each storing a respective computational weight, the method comprising, during a calibration step:

• receiving a plurality of calibration input values and, in response thereto and as a function of the plurality of the calibration input values, providing a plurality of calibration activation signals to the plurality of word lines;
• providing, to the bit line, a calibration bias voltage as a function of a common bias signal;
• detecting an actual computational result as a function of a bit line current that flows in the bit line during the calibration step, wherein the actual computational result is indicative of the charge flowing in the bit line during the calibration step;
• wherein the memory cells are configured to each be traversed by a respective cell current that is a function of the calibration bias voltage, the calibration activation signal received from the respective word line and the respective computational weight;
• wherein the bit line current is a function of a sum of the cell currents of the memory cells coupled to the bit line;
• and
• determining the calibration factor as a function of the error between the actual computational result and an ideal computational result, wherein the ideal computational result is representative of the charge that would have flowed in the bit line during the calibration step in case the computational weights actually stored in the memory cells coupled to the bit line correspond to respective nominal computational weights.