Memory device with adaptive write control and associated method

A memory device comprising:

• a plurality of bit cells arranged in a matrix of rows and columns;
• a plurality of bit lines, each bit line connected to the bit cells in a respective column of bit cells;
• a plurality of bit-bar lines, each bit-bar line connected to the bit cells in a respective column of bit cells;
• a plurality of word lines, each word line connected to the bit cells in a respective row of bit cells;
• a plurality of write driver lines, each write driver line selectively connectable to a bit line or a bit-bar line of at least one respective column of bit cells;
• a plurality of write driver line switches to selectively connect a respective write driver line to ground;
• a plurality of boost capacitors, each boost line capacitor connected to a respective write driver line to selectively inject a negative charge thereon;
• and
• a plurality of adaptive control transistors, each adaptive control transistor connected to a respective write driver line to automatically siphon off some of the negative charge thereon when a voltage applied to a gate of the adaptive control transistor equals or exceeds a threshold voltage of the adaptive control transistor.