Memory device

A memory device, comprising:

• a memory array including a plurality of memory cells arranged in rows and columns;
• a plurality of word lines connected to the memory cells of respective rows of the memory array;
• and
• a plurality of word line driver circuits configured to output word line enable signals to respective ones of the word lines,
• wherein each word line driver circuit comprises:
• an inverter circuit including a first PMOS transistor and a first NMOS transistor;
• an enable transistor including a PMOS FinFET having fewer than 10 fingers;
• and
• a metal line electrically connecting the inverter circuit, the enable transistor, and a corresponding one of the word lines,
• wherein the metal line includes:
• a front side interconnect structure on or over a front side of a substrate;
• a back side interconnect structure on or over a back side of the substrate opposite the front side;
• and
• an interlayer via extending through the substrate and electrically connecting the front side interconnect structure and the back side interconnect structure.

A semiconductor device, comprising:

• a first semiconductor tier;
• a second semiconductor tier over the first semiconductor tier;
• a word line;
• a word line driver circuit configured to output a word line enable signal to the word line, the word line driver circuit including:
• a PMOS transistor of an inverter circuit disposed in the first semiconductor tier;
• an NMOS transistor of the inverter circuit disposed in the second semiconductor tier;
• an enable PMOS transistor disposed in the second semiconductor tier;
• and
• a conductive path electrically connecting the inverter circuit, the enable PMOS transistor, and the word line,
• wherein the conductive path includes:
• a front side interconnect structure;
• a back side interconnect structure;
• and
• an inter-tier conductive via, wherein the conductive path extends through both the front side interconnect structure and the back side interconnect structure.