Enhanced valley tracking with trim setting updates in a memory device
AssigneeMicron Technology, Inc.
InventorsChing-Huang Lu, Yingda Dong
Life of this patent
Estimating the term…
Abstract
Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and performs a first coarse valley tracking calibration operation on the segment of the memory array. The control logic further configures a read voltage level and one or more parameters associated with the read operation based on a result of the first coarse valley tracking calibration operation and performs a second fine valley tracking calibration operation on the segment of the memory array using the configured read voltage level and the configured one or more parameters.
Claims20
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- receiving a request to perform a read operation to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored;
- performing a failed byte count read operation on the segment of the memory array to determine a failed byte count;
- configuring a read voltage level and one or more parameters associated with the read operation based on the failed byte count;
- and
- performing a parallel auto-read calibration (pARC) operation on the segment of the memory array on the segment of the memory array using the configured read voltage level and the configured one or more parameters.
A method comprising:
- receiving a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored;
- performing a failed byte count read operation on the segment of the memory array to determine a failed byte count;
- configuring a read voltage level and one or more parameters associated with the read operation based on the failed byte count;
- and
- performing a parallel auto-read calibration (pARC) operation on the segment of the memory array on the segment of the memory array using the configured read voltage level and the configured one or more parameters.
A memory device comprising:
- a memory array comprising memory cells configured as multi-level cells programmed to a plurality of program voltage levels;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- receiving a request to perform a read operation to read data from the memory array;
- performing a parallel auto-read calibration (pARC) operation on a segment of the memory array, wherein performing the pARC operation comprises performing a sequence of read operations at different read voltage levels and generating a histogram representing error counts from the sequence of read operations to identify a mid-point of a valley between two adjacent programming distributions;
- and
- performing the read operation on the segment of the memory array based on a result of the pARC operation.
Dependencies are inferred from the claim text.