Compute in memory (cim) memory array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYen-An Chang, Yu-Lin Chen, Chia-Fu Lee
Life of this patent
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Abstract
A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
Claims20
A memory device for compute-in-memory (CIM), comprising:
- a memory array including a plurality of memory cells arranged in an array of rows and columns, the plurality of memory cells including a first group of memory cells and a second group of memory cells;
- and
- a control circuit configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal;
- a first sense amplifier coupled to bit lines of the first group of memory cells;
- a second sense amplifier coupled to bit lines of the second group of memory cells;
- and
- a multiplexer (MUX) connected to the first sense amplifier and the second sense amplifier;
- wherein, responsive to the control circuit selecting the first group of memory cells, and an associated bit line is driven to a desired value to selectively write CIM weight values to the first group of memory cells and simultaneously perform a read or write operation on the second group of memory cells.
A memory device for compute-in-memory (CIM), comprising:
- a memory array including a plurality of memory cells arranged in an array of rows and columns, the plurality of memory cells including a first group of memory cells and a second group of memory cells;
- and
- a multiply circuit configured to receive weight signals stored in a selected group of memory cells and multiply the weight signals by a CIM input signal to generate a plurality of partial products;
- wherein, responsive to a select signal selecting the selected group of memory cells, the multiply circuit performs a read or write operation on the first group of memory cells and a simultaneous read or write operation on the second group of memory cells in the memory array.
A method, comprising:
- providing a memory array having a plurality of memory cells arranged in an array of rows and columns, the plurality of memory cells including a first group of memory cells and a second group of memory cells;
- performing a read operation on the first group of memory cells in response to a group enable signal;
- and
- performing, simultaneously to performing the read operation on the first group of memory cells, a write operation on the second group of memory cells in response to the group enable signal.
Dependencies are inferred from the claim text.