Memory device including bit line sense amplifier and operating method thereof

A method of operating a memory device comprising a bit line sense amplifier and a power switch circuit, the method comprising the bit line sense amplifier:

• performing an active operation;
• performing a leakage current reduction operation;
• and
• performing a precharge operation,
• wherein the bit line sense amplifier comprises a plurality of NMOS transistors and a plurality of PMOS transistors, and
• wherein the performing the leakage current reduction operation comprises the power switch circuit reducing a leakage current in the bit line sense amplifier by dynamically controlling one of a body voltage of the plurality of NMOS transistors and a body voltage of the plurality of PMOS transistors.

A memory system comprising:

• a memory controller comprising a power switch control circuit;
• and
• a memory device comprising a power switch circuit and a bit line sense amplifier,
• wherein the bit line sense amplifier comprises a plurality of NMOS transistors and a plurality of PMOS transistors, and
• wherein the power switch circuit is configured to reduce a leakage current in the bit line sense amplifier by dynamically controlling one of a body voltage of the plurality of NMOS transistors and a body voltage of the plurality of PMOS transistors based on a plurality of enable signals received from the power switch control circuit.