Structure and method for in-memory logic gates using gain-cell embedded dram (gc-edram)

A method of manufacture of a device comprising a gain cell (GC) embedded dynamic random access memory (eDRAM)memory array for enabling processing-in-memory (PIM) operations, the method comprising:

• providing a memory circuit in which GC eDRAM cells are arranged in columns between respective read bit lines and write bit lines;
• adding a transistor for each column respectively, the added transistor connecting between the read bit line and the write bit line of the respective column, such that the transistor when enabled provides a conducting path between the read and write bit lines, thereby connecting between an input node and an output node of a currently addressed cell of the respective column.

A device comprising gain cell (GC) embedded dynamic random access memory (eDRAM), the device comprising:

• an array of GC eDRAM bit cells arranged in columns and rows, adjacent rows being designated odd rows and even rows respectively;
• wherein for each column, connections are provided such that write-bit-lines (WBLs) of bit cells in respective even rows are connected to read-bit-lines (RBLs) of bit cells in respective odd rows;
• and WBLs of bit cells in respective odd rows are connected to RBLs of bit cells in respective even rows.

A method of carrying out logic operations in a gain cell (GC) embedded dynamic random access memory (eDRAM) device, the device having bit cells arranged in rows and columns and having odd rows and even rows, wherein for each column, write-bit-lines (WBLs) of bit cells in even rows are connected to read-bit-lines (RBLs) of bit cells in odd rows;

• and WBLs of bit cells in odd rows are connected to RBLs of bit cells in even rows, the method comprising for a given cell, using a read current of respective inputs as a write current for the respective output, thereby to provide an output which depends on states at said respective inputs.