Controlling the output of a probabilistic-bit spintronic device
AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, Centre National De La Recherche Scientifique, Universite Grenoble Alpes, Institut Polytechnique De Grenoble
InventorsKamal DANOUCHI, Louis HUTIN, Guillaume PRENAT
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Abstract
A process for fabricating a spintronic device includes a magnetic tunnel junction; a bias transistor connected in series with the magnetic tunnel junction; a detection circuit having an input connected to a first detection node and an output for generating a detection signal; the detection circuit including at least a first inverter including a first NMOS transistor and a second PMOS transistor each having: a front gate; a back gate formed by an insulating layer buried in a semiconductor substrate; a control circuit configured to apply a non-zero control voltage to the back gate of at least one of the first or second transistor.
Claims14
A spintronic device (D1) comprising:
- a magnetic tunnel junction (MTJ) having a resistance that fluctuates between at least two distinct resistive states (P, AP) depending on its magnetization;
- a bias transistor (Tpol) connected in series with the magnetic tunnel junction (MTJ);
- the common node between the bias transistor (Tpol) and the magnetic tunnel junction (MTJ) constituting a first detection node (NC1);
- a detection circuit (DET) having an input (edet) connected to the first detection node (NC1) and an output (sdet) for generating a detection signal (Vout);
- the detection circuit (DET) comprising at least a first inverter (INV1) comprising a first NMOS transistor (TINV1,N) and a second PMOS transistor (TINV1,P) that are connected in series between electrical ground (GND) and a supply node supplying a supply voltage (VDD), and each having:
- a front gate (G1,N G1,P);
- a back gate (G2,N G2,P) formed by an insulating layer (BOX) buried in a semiconductor substrate;
- the front gates (G1,N G1,P) of the first and second transistor (TINV1,N TINV1,P) receiving the potential (VDIV) of the first detection node (NC1) or an intermediate signal (Vint) generated from the potential (VDIV) of the first detection node (NC1);
- a control circuit (CONT) configured, in a first configuration (CONF1), to apply a non-zero control voltage (Vcmd) to the back gate (G2,N G2,P) of at least one of the first or second transistor (TINV1,N TINV1,P) in order to set the detection signal (Vout) to electrical ground (GND) or to the voltage of the supply node (VDD), depending on the sign of the control voltage (Vcmd).
Dependencies are inferred from the claim text.