Reducing capacitive loading of memory system based on switches
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang, Yih Wang, Yi-Ching Liu
Life of this patent
Estimating the term…
Abstract
Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
Claims20
A device, comprising:
- a first memory array comprising a first subset of memory cells;
- a second memory array comprising a second subset of memory cells;
- wherein the first memory array and the second memory array are stacked on top of each other along a vertical direction;
- and
- wherein the first subset of memory cells are coupled to a first switch and a second switch that are arranged on opposite sides of the first subset of memory cells along the vertical direction, and the second subset of memory cells are coupled to a third switch and a fourth switch that are arranged on opposite sides of the second subset of memory cells along the vertical direction.
A device, comprising:
- a first memory array comprising a plurality of first subsets of memory cells arranged across a first lateral direction and a second lateral direction, each of the plurality of first subsets of memory cells arranged along a vertical direction;
- a second memory array comprising a plurality of second subsets of memory cells arranged along the first lateral direction and the second lateral direction, each of the plurality of second subsets of memory cells arranged along the vertical direction;
- wherein the first memory array and the second memory array are stacked on top of each other along the vertical direction;
- and
- wherein each of the first subsets of memory cells are coupled to a first switch and a second switch that are arranged on opposite sides of the corresponding first subset of memory cells along the vertical direction, and each of the second subsets of memory cells are coupled to a third switch and a fourth switch that are arranged on opposite sides of the corresponding second subset of memory cells along the vertical direction.
A device, comprising:
- a first memory array comprising a plurality of first subsets of non-volatile memory cells arranged across a first lateral direction and a second lateral direction, each of the plurality of first subsets of non-volatile memory cells arranged along a vertical direction;
- a second memory array comprising a plurality of second subsets of non-volatile memory cells arranged along the first lateral direction and the second lateral direction, each of the plurality of second subsets of non-volatile memory cells arranged along the vertical direction;
- wherein the first memory array and the second memory array are stacked on top of each other along the vertical direction;
- and
- wherein each of the first subsets of non-volatile memory cells are coupled to a first switch and a second switch that are arranged on opposite sides of the corresponding first subset of non-volatile memory cells along the vertical direction, and each of the second subsets of non-volatile memory cells are coupled to a third switch and a fourth switch that are arranged on opposite sides of the corresponding second subset of non-volatile memory cells along the vertical direction.
Dependencies are inferred from the claim text.