Integrated circuit with analog in-memory compute

Abstract

An integrated circuit comprising a plurality of cluster chiplets vertically stacked, each of the cluster chiplets comprising a plurality of tiles laterally arranged, each of the tiles comprising at least one processor core coupled to a cache, an analog in-memory compute (AIMC) device coupled to the at least one processor core, a digital access subsystem coupled to the AIMC device, and a cluster bus coupled to the digital access subsystem, and a system bus coupled to the cluster bus of each of the plurality of tiles, and at least one cache chiplet vertically stacked with the plurality of cluster chiplets, wherein the at least one cache chiplet is arranged between a pair of adjacent cluster chiplets from the plurality of cluster chiplets.

Dependencies are inferred from the claim text.