Hybrid cache coherency
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
Estimating the term…
Abstract
To implement a hybrid of software and hardware coherency management, a device can receive an unrestricted-access read request for memory that corresponds to a cache line from a first host and record an indication of the unrestricted-access read request with respect to the cache line. Here, the indication can include an identifier for the first host. However, if the device receives a shared-access read request for the cache line from a second host, the device does not record an identifier of the second host. Rather, the device can communicate an invalidation request for the cache line to the first host using the identifier for the first host to provoke the first host to write-back the data and invalidate the cache line.
Claims20
A memory controller comprising:
- a first interface configured to communicate with multiple host devices, the first interface implementing a Compute Express Link (CXL) family of standards;
- a second interface configured to communicate on an interlink with memory;
- a cache for the memory;
- a storage device;
- and
- processing circuitry configured to:
- receive, via the first interface from a first host, a SHARED request for the memory that corresponds to a cache line in the cache;
- write a meta state in the storage device that indicates the cache line is shared, wherein the meta state does not track an identifier for the first host;
- receive, via the first interface from a second host, an ANY request for the memory and corresponding to the cache line;
- update, based on the ANY request, the meta state in the storage device for the cache line to indicate that the second host has exclusive access including recording an identifier for the second host;
- and
- communicate, based on the ANY request, that the cache line was shared to enable the second host to notify the first host of changes to the cache line.
A non-transitory machine-readable medium including instructions that, when executed by processing circuitry of a memory controller, cause the processing circuitry to perform operations :
- receiving, via a first interface of the memory controller and from a first host, a SHARED request for a memory that corresponds to a cache line in a cache of the memory controller, the first interface configured to communicate with multiple host devices, the first interface implementing a Compute Express Link (CXL) family of standards, the memory controlled by the memory controller via an interlink accessed by a second interface of the memory controller;
- writing a meta state in a storage device of the memory controller, the meta state indicating that the cache line is shared, wherein the meta state does not track an identifier for the first host;
- receiving, via the first interface from a second host, an ANY request for the memory and corresponding to the cache line;
- updating, based on the ANY request, the meta state in the storage device for the cache line to indicate that the second host has exclusive access including recording an identifier for the second host;
- and
- communicating, based on the ANY request, that the cache line was shared to enable the second host to notify the first host of changes.
Dependencies are inferred from the claim text.