Delay operations in processor cores for power improvements
AssigneeQUALCOMM Incorporated
InventorsDinesh Kumar CHOUDHARY, Sai Sneha Venkata YESANTARAO, Sai Sumanth MANCHUKONDA, Maulik SHAH
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Abstract
Aspects of the disclosure are directed to delay operations in processor cores. In accordance with one aspect, the disclosure includes enabling a timer interrupt associated with a delay value; configuring a low power mode (LPM) based on the delay value; executing an idle state entry sequence based on the LPM to transition from an operational state to an idle state; and firing an interrupt signal after a timer expiration.
Claims20
A method comprising:
- enabling a timer interrupt associated with a delay value;
- configuring a low power mode (LPM) based on the delay value;
- executing an idle state entry sequence based on the LPM to transition from an operational state to an idle state;
- and
- firing an interrupt signal after a timer expiration.
An apparatus comprising:
- a non-transitory memory configured to store a delay value;
- and
- a processor coupled to the non-transitory memory, the processor configured to program a low power mode (LPM) based on the delay value and to execute an idle state entry sequence based on the LPM to transition from an operational state to an idle state.
A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement a delay operation, the computer executable code comprising:
- instructions for causing a computer to enable a timer interrupt associated with a delay value;
- instructions for causing the computer to configure a low power mode (LPM) based on the delay value;
- instructions for causing the computer to execute an idle state entry sequence based on the LPM to transition from an operational state to an idle state;
- and
- instructions for causing the computer to fire an interrupt signal after a timer expiration.
Dependencies are inferred from the claim text.