Memory architecture for block migration in zns
AssigneeMicron Technology, Inc.
InventorPaul Stonelake
Life of this patent
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AssigneeMicron Technology, Inc.
InventorPaul Stonelake
Estimating the term…
The disclosure configures a memory sub-system controller to efficiently perform block migration (e.g., from SLC cache to QLC blocks) in a Zone Namespace (ZNS) device. The controller associates a plurality of zones of the set of memory components with a plurality of internal zone groups (IZGs) each associated with a different write cursor. The controller programs data to a first portion of a set of memory components using the plurality of write cursors, the first portion being associated with a first type of storage, and determines that an individual IZG of the plurality of IZGs satisfies a migration criterion. The controller migrates a portion of the data stored in the first portion of the set of memory components corresponding to the individual IZG to a second portion of the set of memory components, the second portion of the set of memory components being associated with a second type of storage.
A system comprising:
A method comprising:
A non-transitory computer-readable storage medium comprising instructions that, when executed by at least one processing device, cause the at least one processing device to perform operations comprising:
Dependencies are inferred from the claim text.