Memory device with asymmetric pass through voltage for read operations

A memory device comprising:

• a memory array comprising memory cells;
• and
• control logic operatively coupled with the memory array, the control logic to perform operations comprising:
• causing, during a read operation, a read voltage level to be applied to a target wordline of the memory array;
• causing, during the read operation, a first pass through voltage level to be applied to a first wordline adjacent to the target wordline;
• and
• causing, during the read operation, a second pass through voltage level to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.

A memory device comprising:

• a memory array comprising memory cells;
• and
• control logic operatively coupled with the memory array, the control logic to perform operations comprising:
• determining a program verify voltage level to be applied to a target wordline of the memory array during a program verify operation;
• in response to determining the program verify voltage level is a lowest program verify voltage level, causing a symmetric pass through voltage level to be applied to a first wordline adjacent to the target wordline and a second wordline adjacent to the target wordline;
• and
• in response to determining the program verify voltage level is greater than the lowest program verify voltage level, causing an asymmetric pass through voltage level to be applied to the first wordline and the second wordline, wherein a first pass through voltage level applied to the first wordline is less than a second pass through voltage level applied to the second wordline.