Memory device including clock signal correction circuit, memory system, and operating method of memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsWonmuk Lim, Seunghwan Hong
Life of this patent
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Abstract
A memory device includes a clock signal correction circuit, a memory system, and an operating method of the memory device. The memory device may include a first correction circuit configured to adjust phases of first to fourth clock signals and output first to fourth corrected clock signals, a second correction circuit configured to output first to fourth offset clock signals based on a size of each of first to fourth reference data included in a first data signal, and a driver configured to output a second data signal based on the first to fourth corrected clock signals.
Claims20
A memory device comprising:
- a memory cell array storing a plurality of data;
- a first correction circuit configured to receive a plurality of clock signals and a control signal, adjust phases of the plurality of clock signals based on the control signal, and output a plurality of corrected clock signals;
- a second correction circuit configured to receive the plurality of clock signals through the first correction circuit, adjust the phases of the plurality of clock signals based on a difference between an interval of a first reference data of a plurality of reference data included in a first data signal and a reference unit interval, and output a plurality of offset clock signals, the plurality of reference data being associated with the plurality of clock signals;
- a control circuit configured to generate the control signal based on the plurality of offset clock signals received from the second correction circuit;
- and
- a driver configured to output, based on the plurality of corrected clock signals received from the first correction circuit, a second data signal including the plurality of data read from the memory cell array.
An operating method of a memory device, the operating method comprising:
- generating a plurality of clock signals;
- generating a plurality of offset clock signals based on a difference between an interval of a first reference data of a plurality of reference data included in a first data signal and a reference unit interval, the plurality of reference data being associated with the plurality of clock signals;
- generating a plurality of corrected clock signals by adjusting, based on the plurality of offset clock signals, phases of the plurality of clock signals;
- and
- outputting, based on the plurality of corrected clock signals, a second data signal including data stored in the memory device.
A memory system comprising:
- a memory controller configured to generate a first reference clock signal, a second reference clock signal, and a control signal;
- and
- a memory device comprising a memory cell array configured to store a plurality of data, the memory device configured to:
- generate a plurality of clock signals, based on the first reference clock signal and the second reference clock signal;
- provide the memory controller with a first data signal including a plurality of reference data, the plurality of reference data being associated with the plurality of clock signals;
- adjust phases of the plurality of clock signals based on the control signal to generate a plurality of corrected clock signals;
- and
- output, based on the plurality of corrected clock signals, a second data signal including the plurality of data read from the memory cell array,
- wherein the memory controller is further configured to generate the control signal based on a difference between an interval of a first reference data of the plurality of reference data and a reference unit interval.
Dependencies are inferred from the claim text.