Information processing system having improved computational throughput of processing in memory by maximizing memory bandwidth in a multi-channel memory that supports a memory bus interface having limited bandwidth

An information processing system comprising:

• a channel level (CL) burst circuit configured to:
• control a read or write operation between a channel arbiter and a memory controller,
• generate a plurality of CL packets based on a memory packet comprising memory control information received from the channel arbiter and operand attribute (O/A) information stored in the CL burst circuit, and
• transmit the plurality of CL packets to the plurality of memory controllers included in a plurality of channels, respectively,
• wherein the memory controller performs a task in response to receiving a related CL packet, among the plurality of CL packets, and
• a response packet of a CL packet that is not a start packet is invalidated by a memory interface and is not transmitted to a host.