Integrated circuit capable of performing dynamic voltage and frequency scaling operation based on workload and operating method thereof

An operating method of an integrated circuit, the operating method comprising:

• monitoring a shared buffer which comprises a plurality of blocks and obtaining a buffer capacity of the shared buffer, a response waiting time for a response received from an external memory, and an identifier of a first core of a plurality of cores, wherein the shared buffer receives a request including data designating a certain block among the plurality of blocks from the first core, and wherein each of the plurality of blocks is configured to access a corresponding designated region among a plurality of regions of the external memory, the buffer capacity corresponding to a number of respective ones of the plurality of blocks each using a threshold capacity being greater than or equal to a threshold number among the plurality of blocks;
• classifying a workload of the first core based on the buffer capacity and the response waiting time;
• and
• determining a scaling factor for a voltage-frequency level of the first core based on the classified workload of the first core.

A computing system comprising:

• a processor comprising a plurality of cores;
• at least one memory;
• a bus connecting the processor to the at least one memory;
• a dynamic voltage and frequency scaling (DVFS) controller configured to identify a first core of the plurality of cores according to an identifier of the first core, and classify a workload of the first core based on a buffer capacity of a shared buffer and a response waiting time for a response received from the bus, determine a scaling factor based on the classified workload, and generate a voltage control signal and a clock control signal based on the determined scaling factor, the shared buffer comprises a plurality of blocks, wherein each of the plurality of blocks is configured to access a corresponding designated region among a plurality of regions of the at least one memory, the buffer capacity corresponding to a number of respective ones of the plurality of blocks each using a threshold capacity being greater than or equal to a threshold number among the plurality of blocks;
• a power management unit configured to adjust an amplitude of a power supply voltage provided to the first core in response to the voltage control signal;
• and
• a clock management unit configured to adjust a frequency of a clock signal provided to the first core, in response to the clock control signal, wherein
• each of the plurality of cores configured to process an instruction according to the amplitude of the power supply voltage and the frequency of the clock signal;
• the processor further comprising
• the shared buffer configured to receive a request including data designating a certain block among the plurality of blocks from the first core of the plurality of cores, access the bus according to the request, and receive the response from the bus;
• and
• a monitor configured to monitor the shared buffer to obtain the buffer capacity, the response waiting time and the identifier of the first core.