Voltage regulators with shared decoupling capacitor for memory devices

A circuit, comprising:

• a first voltage regulator configured to provide a first operation voltage to a memory macro;
• a second voltage regulator configured to provide a second operation voltage to the memory macro, wherein the first operation voltage, corresponding to a write mode of the memory macro, is higher than the second operation voltage, corresponding to a read mode of the memory macro;
• and
• a decoupling capacitor configured to switch between coupling the first voltage regulator to a ground voltage and coupling the second voltage regulator to the ground voltage.

A circuit, comprising:

• a first voltage regulator configured to provide a first operation voltage to a memory macro;
• a second voltage regulator configured to provide a second operation voltage to the memory macro, wherein the first operation voltage, corresponding to a write mode of the memory macro, is higher than the second operation voltage, corresponding to a read mode of the memory macro;
• a first switch;
• a second switch;
• and
• a decoupling capacitor configured to couple a first output node of the first voltage regulator to a ground voltage when the first switch is activated, or to couple a second output node of the second voltage regulator to the ground voltage when the second switch is activated.