Package-on-package design for improved memory interconnect and thermal management in semiconductor devices
AssigneeQUALCOMM Incorporated
InventorsJungwon SUH, Bernie YANG, Aniket PATIL
Life of this patent
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Abstract
A package-on-package (PoP) semiconductor device has an asymmetrically placed interface interconnect for connecting a top package to a bottom package. The interface interconnect can include a ball-out layout that is concentrated on one lateral side of the top package and/or bottom package. The PoP semiconductor device can include a heat slug on the bottom package to provide improved thermal management. The PoP semiconductor device can optimize interface interconnect routing, enhance thermal management, and achieve a more competitive form factor.
Claims29
A package-on-package (PoP) semiconductor device, comprising:
- a bottom package comprising a first die;
- a top package positioned on the bottom package, the top package comprising one or more second dies;
- and
- an interconnect structure comprising a ball-out layout configured to connect the one or more second dies to the first die, wherein the ball-out layout is an asymmetric ball-out layout that is asymmetric with respect to a mirror axis of at least one of the top package or the bottom package.
A semiconductor device, comprising:
- a top package comprising one or more first dies;
- a bottom package comprising a second die;
- and
- an interconnect structure configured to connect the one or more first dies and the second die,
- wherein the interconnect structure is asymmetrically placed on at least one of the bottom package or the second die.
A method for configuring a package-on-package (PoP) semiconductor device, comprising:
- providing a bottom package comprising a first die;
- providing a top package positioned on the bottom package, the top package comprising one or more second dies;
- and
- providing an interconnect structure configured to connect the one or more second dies to the first die,
- wherein the interconnect structure is an asymmetric interconnect structure that is asymmetric with respect to a mirror axis of at least one of the top package or the bottom package.
A method of configurating a semiconductor device, the method comprising:
- providing a top package comprising one or more first dies;
- providing a bottom package comprising a second die;
- and
- an interconnect structure configured to connect the one or more first dies and the second die,
- wherein the interconnect structure is asymmetrically placed on at least one of the bottom package or the second die.
Dependencies are inferred from the claim text.