US 2026/0305386 A1Published application

Packages with plated die pads, terminals, and inductors

OwnerYou Chye HOW, Huay Yann TAY +1inventors

InventorsYou Chye HOW, Huay Yann TAY, Wei Li JULIEN MOK

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Abstract

A semiconductor package includes a die pad having a top surface, a bottom surface opposite the top surface, and four lateral surfaces orthogonal to the top and bottom surfaces, the top surface of the die pad and the four lateral surfaces of the die pad covered by a first metal; multiple semiconductor terminals, each of which has a top surface, a bottom surface opposite the top surface, and four lateral surfaces orthogonal to the top and bottom surfaces, the top surface of the respective semiconductor terminal and three of the four lateral surfaces of the respective semiconductor terminal covered by the first metal, one lateral surface of the four lateral surfaces of the respective semiconductor terminal not covered by the first metal; a die coupled to the first metal on the top surface of the die pad; and a second metal contacting the bottom surfaces of the multiple semiconductor terminals.

Claims20

Dependent claims

A semiconductor package, comprising:

a semiconductor die pad having a top surface, a bottom surface opposite the top surface, and four lateral surfaces orthogonal to the top and bottom surfaces, the top surface of the semiconductor die pad and the four lateral surfaces of the semiconductor die pad covered by a first metal;
multiple semiconductor terminals, each of the multiple semiconductor terminals having a top surface, a bottom surface opposite the top surface of the respective semiconductor terminal, and four lateral surfaces orthogonal to the top and bottom surfaces of the respective semiconductor terminal, the top surface of the respective semiconductor terminal and three of the four lateral surfaces of the respective semiconductor terminal covered by the first metal, one lateral surface of the four lateral surfaces of the respective semiconductor terminal not covered by the first metal;
a semiconductor die coupled to the first metal on the top surface of the semiconductor die pad, the semiconductor die having a device side facing away from the semiconductor die pad;
a second metal physically contacting the bottom surfaces of the multiple semiconductor terminals;
bond wires coupled to the device side of the semiconductor die and to the first metal on the top surfaces of the multiple semiconductor terminals;
and
a mold compound physically contacting the first metal on the top surface of the semiconductor die pad, the first metal on the top surfaces of the multiple semiconductor terminals, the semiconductor die, and the bond wires.

4 more elements

A semiconductor package, comprising:

a semiconductor member having a die pad portion, a terminal portion, and an intervening portion in between the die pad portion and the terminal portion;
a first metal member covering a top surface of the die pad portion and four lateral surfaces of the die pad portion orthogonal to the top surface of the die pad portion;
a second metal member covering a top surface of the terminal portion and three lateral surfaces of the terminal portion orthogonal to the top surface of the terminal portion;
first multiple metal members in the intervening portion and extending parallel to a surface of the die pad portion that faces the terminal portion;
second multiple metal members in the intervening portion and coupling the first multiple metal members to each other at approximately right angles, the first and second multiple metal members together forming an inductor;
a semiconductor die coupled to the die pad portion;
a bond wire coupled to the semiconductor die and the terminal portion;
and
a mold compound physically contacting the semiconductor member, the first and second metal members, the first and second multiple metal members, the semiconductor die, and the bond wire.

6 more elements

A method for manufacturing a semiconductor package, comprising:

plasma etching a semiconductor wafer using a patterned first photoresist to produce a semiconductor die pad and multiple semiconductor terminals surrounding the semiconductor die pad, the semiconductor die pad attached to the multiple semiconductor terminals;
removing the first photoresist;
covering top and lateral surfaces of the semiconductor die pad and the multiple semiconductor terminals with a seed layer;
electroplating the seed layer to produce a plated layer;
coupling a semiconductor die to a portion of the plated layer on the top surface of the semiconductor die pad;
coupling bond wires to the semiconductor die and to portions of the plated layer on the top surfaces of the multiple semiconductor terminals;
covering the semiconductor die pad and the multiple semiconductor terminals with a mold compound;
thinning the semiconductor wafer by back grinding;
applying a metal layer to a backside of the semiconductor wafer;
using a patterned second photoresist to etch the metal layer;
removing the second photoresist;
and
singulating the semiconductor wafer through the multiple semiconductor terminals to produce the semiconductor package.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/096,284Filed 31 Mar 2025
Published: 1 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 70/479
Leadframes: on or in insulating or insulated package substrates, interposers, or redistribution layers
H10W 70/05
Manufacture or treatment: of insulating or insulated package substrates, or of interposers, or of redistribution layers
H10W 70/66
Characterised by their interconnections: conductive materials thereof
H10W 70/698
Insulating materials thereof: semiconductor materials that are electrically insulating, e.g. undoped silicon