Semiconductor Device Structure Having a Multi-Layer Conductive Feature and Method Making the Same

A method comprising:

• depositing an etch stop layer;
• depositing an interlayer dielectric layer over the etch stop layer;
• patterning the interlayer dielectric layer and the etch stop layer form an opening therein that exposes a tungsten-comprising top surface of a lower interconnect;
• depositing a ruthenium-comprising layer in the opening over the tungsten-comprising top surface of the lower interconnect without depositing the ruthenium-comprising layer over a top surface of the interlayer dielectric layer;
• depositing a metal-comprising liner in the opening over the ruthenium-comprising layer and over the top surface of the interlayer dielectric layer, wherein a first metal of the metal-comprising liner is different from ruthenium and tungsten;
• depositing a metal-comprising layer in the opening over the metal-comprising liner and over the top surface of the interlayer dielectric layer, wherein a second metal of the metal-comprising layer is different from ruthenium and tungsten;
• and
• performing a planarization process that removes the metal-comprising layer and the metal-comprising liner from the top surface of the interlayer dielectric layer, wherein the ruthenium-comprising layer, the metal-comprising liner, and the metal-comprising layer combine to form an upper interconnect on the lower interconnect.

A method comprising:

• forming a source/drain contact;
• forming a first plurality of dielectric layers of a via level of an interconnect structure over the source/drain contact, wherein the first plurality of dielectric layers includes a first etch stop layer and a first interlayer dielectric layer;
• forming a metal via in the first plurality of dielectric layers, wherein the metal via extends through the first plurality of dielectric layers to the source/drain contact;
• forming a second plurality of dielectric layers of a metal line level of the interconnect structure over the metal via, wherein the second plurality of dielectric layers includes a second etch stop layer and a second interlayer dielectric layer;
• and
• forming a metal line in the second plurality of dielectric layers, wherein the metal line extends through the second plurality of dielectric layers to the metal via and the forming the metal line in the second plurality of dielectric layers includes:
• forming an opening in the second plurality of dielectric layers that exposes the metal via in the first plurality of dielectric layers,
• bottom-up depositing a first metal layer on the metal via, wherein the first metal layer completely fills a lower portion of the opening,
• depositing a second metal layer that covers a top of the first metal layer, wherein the second metal layer partially fills and lines sidewalls of an upper portion of the opening, and
• depositing a third metal layer on the second metal layer, wherein the third metal layer fills a remainder of the upper portion of the opening.